L64724 LSI Logic Corporation, L64724 Datasheet - Page 256

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L64724

Manufacturer Part Number
L64724
Description
Satellite Receiver
Manufacturer
LSI Logic Corporation
Datasheet

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B-42
Group 4, APR 53 – Set to 0x38.
Set the bits in the Clock Loop Configuration register (APR 53) as shown
in
Table B.10
Group 4, APR 54 – Set to 0x00.
Set the bits in the Demodulator Configuration register (APR 54) as
shown in
L64724 Application Notes
Bits
D7
D6
D5
D4
D3
D2
D1
D0
Table
Setting
B.10.
Table
0
0
1
1
1
0
0
0
Clock Loop Configuration Register Bits
B.11.
CLK_ERROR_SWAP
CLK_SWP_SWAP
CLK_AUTO_SWP
AGC_CLK_SEL
CLK_OPEN
Acronym
Reserved
Reserved
CLK_SW
Meaning
Not significant when auto sweep is
on or when sweep is off
Timing error detector output not
inverted
Automatic internal sweep control
Set this bit to 1
Integrate over all samples
Clear this bit to 0
Enable the clock loop
Clock sweep off

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