L64724 LSI Logic Corporation, L64724 Datasheet - Page 34

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.1.1 Parallel Host Interface Mode
3-4
1. Serial Mode is the recommended interface mode. LSI Logic does not recommend parallel
mode for new designs.
The L64724 has an internal 8-bit architecture. Most registers are 8 bits
wide, while some are either 16 or 24 bits wide. All registers are
memory-mapped to the system with 8-bit resolution. When you are
accessing a register that is wider than 8 bits, you must read or write two
or three 8-bit sections. The sections are divided into the least-significant
byte (LSB), the middle-significant byte (MB), and the most-significant
byte (MSB). Each 8-bit section is assigned a specific address, and
requires an individual memory cycle during programming.
The L64724 is addressable through either a serial or a parallel host
interface. The interface used depends on the state of the HOST_MODE
input pin when the L64724 is reset. The interface is selected as follows:
The interface mode cannot be changed once the part is in operation. The
following paragraphs show the steps required to read and write the
L64724 registers when you are in Parallel Host Interface mode. Serial
Host Interface mode is discussed in
Mode,” page
Serial Bus
Figure 3.2
through the parallel microprocessor interface.
To read and write registers using the parallel interface mode, follow these
steps:
1. Issue a hard reset to the L64724 for three clock cycles, as shown in
L64724 Registers
HOST_MODE pin HIGH = Parallel Host Interface mode
HOST_MODE pin LOW = Serial Host Interface mode
Figure
cycles, before continuing.
Note:
through
3.2. Wait for the wake-up time (t
Protocol,".
3-6, and
The PCLK signal must operate for the user to be able to
access Groups 2 and 3. Group 4, however, can be
programmed in the absence of PCLK.
Figure 3.5
Appendix A, "Programming the L64724 Using the
1
demonstrate read and write operation
Section 3.1.2, “Serial Host Interface
WK
), which is 280 PCLK