L64724 LSI Logic Corporation, L64724 Datasheet - Page 74

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.9 Viterbi Maximum Bit Error Count, Rate 3/4 (Group 4: APR 10)
3-44
For example, a value of VMBEC_2_3[7:0] = 0x03 specifies 416 errors.
For more information, see
a software reset (FEC_RST, APR 55, bit 0 set to 1) does not affect the
contents of the register.
Read/Write: R/W
This register specifies the maximum number of Viterbi symbol errors that
are allowed to occur within the data period set by VMDC1 (Group 4,
APR 4) to achieve Viterbi module synchronization.
Whenever the symbol error count from the internal bit error counter
exceeds the value VMBEC_3_4[7:0], the synchronization module
concludes that the Viterbi decoder module is out of synchronization and
proceeds to adjust the phase of the incoming symbol stream until
synchronization is reached. The symbol error count is given by
Equation
Equation 3.5
For example, a value of VMBEC_2_3[7:0] = 0b0000.0011 specifies 416
errors. For more information, see
page
does not affect the contents of the register.
Read/Write: R/W
L64724 Registers
APR
APR
10
9
Number of Symbol Errors
Note:
7-7. Note that a software reset (FEC_RST, APR 55, bit 0 set to 1)
D7
D7
3.5.
This register is used during Viterbi code rate acquisition for
Rate 3/4.
Viterbi Maximum Bit Error Count VMBEC_2_3[7:0], Rate 2/3
Viterbi Maximum Bit Error Count VMBEC_3_4[7:0], Rate 3/4
Section 7.1.3, “Viterbi BER Monitor.”
=
128 VMBEC_3_4
Section 7.1.3, “Viterbi BER Monitor,”
+
32
Note that
D0
D0