L64724 LSI Logic Corporation, L64724 Datasheet - Page 106

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.46 SPI_Gain[9:0] (Group 4: APR 64 and 65)
3.6.47 SPI_Bias (Group 4: APR 66, 67, and 68)
3-76
This register sets the gain of the SPI Byte Clock generation loop.
Read/Write: R/W
The SPI_Gain[9:0] value is used to control the loop gain in the SPI Byte
Clock generation module. Typical values are 100 for high data rates (no
decimation and decimation by 2), 50 for decimation by 4, 25 for
decimation by 8, and 10 for decimation by 16.
This register sets the bias of the SPI Byte Clock generation loop.
Read/Write: R/W
This 23-bit value is determined by
rounded to the closest integer.
Equation 3.9
The terms in
Bias = SPI_Bias[22:0]
VCR = Viterbi Code Rate
L64724 Registers
APR
APR
APR
APR
APR
66
67
68
64
65
Bias
Reserved
=
D15
D15
D23
D7
D7
2
---------------------------------------------------- -
24
Equation 3.9
VCR F
F
D22
sample
symbol
Reserved
have the following meanings:
SPI_Bias[15:8]
SPI_Gain[7:0]
SPI_Bias[7:0]
Equation
SPI_Bias[22:16]
3.9. The value must be
D10
D2
SPI_Gain[9:8]
D1
D9
D16
D0
D8
D0
D8