L64724 LSI Logic Corporation, L64724 Datasheet - Page 259

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

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Table B.14
(Sheet 1 of 4)
APR
[5:0]
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
Set to 1
IMQ
D7
Viterbi Code Rate[2:0]
Low Data Rate Register Values
Reserved
In the equation, VCR = 3/4 and OR = 60e6/2e6, so SPIBias = 419430
(0x06.6666).
Set Group 4, APR 68 to 0x06, APR 67 to 0x66, and APR 66 to 0x66.
Group 4, APR 69 – Set to 0x4B.
Set the timing lock threshold (CLK_LC_THSL[7:0]) value at 75 (0x4B.)
Table B.14
QPSK Demodulator and FEC Configuration Example: Low Data Rates
served
Viterbi Max Data Bit Count 2, VMDC2[15:8], middle byte
DVB_
Viterbi Max Data Bit Count 2, VMDC2[23:16], high byte
DSS
Re-
D6
Viterbi Max Data Bit Count 2, VMDC2[7:0], low byte
Viterbi Maximum Bit Error Count[7:0], Rate 1/2
Viterbi Maximum Bit Error Count[7:0], Rate 2/3
Viterbi Maximum Bit Error Count[7:0], Rate 3/4
Viterbi Maximum Bit Error Count[7:0], Rate 5/6
Viterbi Maximum Bit Error Count[7:0], Rate 6/7
Viterbi Maximum Bit Error Count[7:0], Rate 7/8
Viterbi Max Data Bit Count, VMDC1[7:0]
gives the register values calculated for low data rates.
QB
D5
Synchronization Word[7:0]
TEI
D4
SYNC2
_MOD
D3
PLL_N[5:0]
PLL_S[5:0]
PLL_T[4:0]
Reserved
D2
D1
PLL_M[1:0]
DO
HEX
1E
81
04
01
09
40
00
00
00
00
00
00
00
00
47
B-45