L64724 LSI Logic Corporation, L64724 Datasheet - Page 235

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Equation B.32
Set Group 4 APR 44 to 0x0F and APR 43 to 0xA0.
Group 4, APR 45–46 – Set to 0x0600.
The value for the upper sweep limit, CLK_USWL[15:0], is set as
explained in the following paragraphs. It should be noted that the upper
sweep limit is an approximate value but the approximation to the real
sweep limit is accurate enough. Assume that the upper sweep limit
needed is +10 kHz. CLK_USWL[15:0] is calculated as shown in
B.33.
Equation B.33
Set Group 4, APR 46 to 0x06 and APR 45 to 0x00.
Group 4, APR 47–48 – Set to 0xFA00.
The value for the lower clock sweep limit, CLK_LSWL[15:0], is set as
explained in the following paragraphs. It should be noted that the lower
sweep limit is an approximate value, but the approximation to the real
sweep limit is accurate enough. Assume that the lower sweep limit
needed is 10 kHz. The CLK_LSWL[15:0] value is calculated as shown
in
Equation B.34
QPSK Demodulator and FEC Configuration Example: High Data Rates
Equation
CLK_SWR
CLK_SWR
CLK_USWL
CLK_LSWL
CLK_USWL
B.34.
=
=
=
=
=
2
-----------------------------------------------------------------------------
2
-------------------------------------------------------- -
F s
------------------------------------------------------ - 2
50.0 10
45
45
---------------------------------------------------------- -
F s
------------------------------------------------------ -
50.0 10
2
2
45
45
50.0 10
2
1 10
sweeprat e T
------------------------ -
DF_Ratio
45
---------------------------- -
DF_RATIO
–
sweeplimit
6
1
10 10
10
6
1
6
1
6
1
-------------------------- -
21.3 10
10
1 16
16
3
3
2
2
1
22
2
22
22
=
2
6
2
1536
=
2
–
=
1536
(0x0600)
4000
(0xFA00)
(0xFA0)
Equation
B-21