L64724 LSI Logic Corporation, L64724 Datasheet - Page 177

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

7.1.3 Viterbi BER Monitor
Figure 7.4
Symbol 1
Symbol 0
Depuncture
Module
Block Diagram of Viterbi Bit Error Detection Circuit
Configuration
Parameter
A performance monitor for the channel BER is built into the L64724. The
monitor compares an appropriately delayed version of the incoming
channel data stream to the re-encoded Viterbi decoder output data
stream to find occurrences of bit errors.
the Viterbi bit error detection circuit.
The decoder processes the bit error events further to produce a measure
of the actual channel bit error rate. The register VMDC2 (Group 4,
APR 5–7) specifies the number of channel bits (and therefore the time
period), divided by four, over which the decoder counts the number of
occurring channel bit errors. Refer to
Count 2 (Group 4: APR 5, 6, and 7),” page
VMDC2.
The channel data error counter accumulates the errors internally and
updates the Viterbi Bit Error Rate Count (VBERC, Group 3, APR 4:5)
once at the end of the period specified by VMDC2. You can read the
value of the VBERC using the microcontroller interface. VBERC contains
the number of errors divided by four. In addition, the L64724 sets the
VBER flag in the System Status Register (Group 2.) The VBER flag
indicates that the decoder has reached the period specified by VMDC2.
Viterbi Decoder Module
Depunctured
Data
Max Data
Bit Count
(VMDC2)
Rate = 1/2
Decoder
Viterbi
Core
24
Channel Data
Comparator
Error Count
Section 3.6.6, “Viterbi Max Data Bit
Figure 7.4
3-42, for a description of
Bit Error
16
Count
is a block diagram of
Decoded Data
7-7