L64724 LSI Logic Corporation, L64724 Datasheet - Page 116

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

4.1 Data Control and Clocking Schemes
4-2
The L64724 uses the CLK input clock signal to accommodate a number
of possible configurations in a channel decoding system. An external
crystal oscillator generates the CLK signal. An on-chip PLL derives the
PCLK sampling signal from the CLK signal. The PCLK signal operates
the ADC, demodulator, and FEC modules. LCLK is generated by dividing
the CLK signal by the CLK_DIV parameter.
Note that due to the demodulator architecture chosen, the output data
stream always exhibits a certain degree of burstiness.
Figure 4.1
QVIN
Channel Interfaces and Data Control
IVIN
L64724
L64724 Clocking: Internal PLL
ADC
OSC
PLL
CLK
PCLK
Demodulator
CLK_DIV2
DEMQ
DEMI
LCLK
PCLK
FEC