L64724 LSI Logic Corporation, L64724 Datasheet - Page 274

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

D.2.1 Analog Input Impedance
D.2.2 Analog Input Range
D.2.3 Reference Voltage
D.2.4 External Bias Current
D-4
It is recommended that the filter components connected to the
ADCVDDQ/ADCVSSQ and ADCVDDI/ADDVSSI pins be placed in close
proximity to their respective pins.
The analog input (IVIN, QVIN) capacitance is specified to be typically
10 pF. No input resistance is specified because the input is connected to
the gate of a FET or an array of FETs. The DC resistance for the input
is very high (millions of ohms), only degraded by leakage current.
However, due to the capacitance, the input impedance decreases with
increase in input frequency. The source impedance should be kept as
low as possible.
The recommended analog input range is from 0 to 1 V. The actual top of
the range is set by the voltage at ADCVREFI (ADCVREFQ), which is
recommended to be 1 V. The actual bottom of the range is the voltage
at ADCVREFIN (ADCVREFQN), which is 0 V, or analog ground.
While it is possible to set up the Analog Input Range to be different from
the 0 to 1 V range, be aware that if ADCVREFI (ADCVREFQ) is
decreased from 1 V, the linearity of the A/D suffers. It is not
recommended that the voltage be more than 10% above 1 V. The
L64724 internally generates the DC offset for the Analog Input (IVIN,
QVIN).
The L64724 internally generates the reference voltage for the dual ADCs.
The external bias current is recommended to be 50 A, which is the bias
current for the array of differential pair FET comparators inside the
A/D converter. The external resistor sinks the bias current.
A/D Converters