L64724 LSI Logic Corporation, L64724 Datasheet - Page 41

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

APR
0
VBER_IE
D7
S3_LS_IE
The following register diagram shows the bit organization of SMR[7:0].
Descriptions of the bits follow the register diagram. The L64724 clears
all bits in the SMR to zero after a software or hardware reset.
VBER_IE
S3_LS_IE
S3_S_IE
Group 2: System Mode and System Status Registers
D6
S3_S_IE
D5
Viterbi Bit Error Rate Monitor Interrupt Enable
The microprocessor sets the VBER_IE bit to enable an
interrupt when the Viterbi decoder reaches the period
specified by VMDC2 (the period over which the Viterbi bit
errors are counted). The L64724 always sets the VBER
bit in the STS register when this condition occurs.
Stage 3 Loss of Synchronization Interrupt Enable
The microprocessor sets the S3_LS_IE bit to enable an
interrupt when Descrambler synchronization is lost.
S3_LS_IE is not used in DSS mode.
Stage 3 Synchronization Interrupt Enable
The microprocessor sets the S3_S_IE bit to enable an
interrupt when Descrambler synchronization is
established. S3_S_IE is not used in DSS mode.
S3_LS_IE
VBER_IE
S3_S_IE
S2_LS_IE
0
1
0
1
0
1
D4
SMR[7:0]
S2_S_IE
Definition
Disable Interrupt for Viterbi BER count
Enable Interrupt for Viterbi BER count
Definition
Disable Interrupt for Stage 3 Loss of
Synchronization
Enable Interrupt for Stage 3 Loss of
Synchronization
Definition
Disable Interrupt for Stage 3
Synchronization
Enable Interrupt for Stage 3 Synchronization
D3
S1_LS_IE
D2
S1_S_IE
D1
Reserved
D0
3-11
7
6
5