L64724 LSI Logic Corporation, L64724 Datasheet - Page 40

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.4.1 System Mode Register (SMR)
Table 3.2
3-10
APR
0
1
2
3
CLK_LK_
VBER_IE
uC_IE7
D7
IE
Group 2 System Mode Register Map (Write-Only)
CLK_LLK_
S3_LS_IE
uC_IE6
The 32-bit System Mode Register (SMR) is a write-only register that
allows the external microprocessor to control the L64724.
shows the SMR map.
The bits in the register are allocated as follows:
Because the SMR is arranged as four 8-bit registers, the microprocessor
must perform four consecutive writes to the register address. The lower
eight bits of the APR must be set to 0x00 in order to access bits
SMR[7:0]. The eight LSBs of the SMR are accessed first. The auto-
increment mechanism toggles the Address Pointer Register after the first
access so that the next write goes to the SMR[15:8] bits.
If you want to access the SMR starting with bytes 1, 2, or 3, set the
APR equal to 0b01, 0b10, or 0b11, respectively.
L64724 Registers
D6
IE
SMR[7:0] enable FEC module interrupts.
SMR[23:8] enable the Demodulator interrupts.
SMR[31:24] enable interrupts for the on-chip microcontroller.
CP_LK_IE CP_LLK_
S3_S_IE S2_LS_IE S2_S_IE S1_LS_IE
uC_IE5
D5
Reserved
uC_IE4
D4
IE
SMR[23:16]
SMR[31:24]
SMR[15:8]
SMR[7:0]
uC_IE3
D3
Reserved = 0
uC_IE2
D2
CL_FS_LL_
TL_FS_LL_
S1_S_IE
uC_IE1
D1
IE
IE
Table 3.2
CL_FS_UL_
TL_FS_UL_
Reserved
uC_IE0
D0
IE
IE