L64724 LSI Logic Corporation, L64724 Datasheet - Page 197

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table 8.6
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Sheet 1 of 2)
t
t
t
t
t
t
t
t
T
t
t
t
t
t
CYCLE
PWH
PWL
S
H
OD
RWH
WK
SURCS
SUA
HLDA
DCSDTL
HLDD
DLY
L64724-75 AC Timing Parameters with Microcontroller Disabled
Description
Clock Cycle for CLK
Clock Pulse Width HIGH
Clock Pulse Width LOW
Input Setup time to CLK
Input Hold to CLK
Output Delay from CLK
RESET Pulse Width HIGH
Wake-Up Time
Delay from COEn
READ Setup Before CSn LOW
A[2:0] Setup Before ASn LOW
A[2:0] Hold After ASn LOW
Data Valid to DTACKn/WAIT
LOW
Write Data Hold After CSn HIGH
Table 8.8
internal microcontroller disabled.
microcontroller enabled. All parameters in the timing tables apply for
T
AC Timing
A
= 0 C to 70 C and a capacitive load of 15 pF.
shows the timing parameters valid for operation with the
Groups 2, 3
Groups 2, 3
Groups 0,
Groups 0,
Register
Groups
1, 4
1, 4
Table 8.9
–
–
–
–
–
–
–
–
–
–
–
–
13.3
15.0
Min
280
6.0
6.0
0.0
0.0
0.0
shows the timing for the
0
4
–
3
–
0
–
75 MHz
Max
15.0
15.0
7.3
7.3
–
–
–
9
–
–
–
–
–
1
–
CLK Cycles
CLK Cycles
CLK Cycles
CLK cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8-9
1
1
1
1