L64724 LSI Logic Corporation, L64724 Datasheet - Page 53

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.5 Group 3: Status Registers
Table 3.4
APR
(Sheet 1 of 2)
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Demod_SNR
Reserved
D7
Group 3 Register Map
Reserved
Reserved
Group 3 consists of a number of internal status registers that are used
for diagnostics and performance evaluation purposes. The registers are
internally updated every PCLK cycle and are read asynchronously. When
the microprocessor reads the register, the current information is buffered
in a special-purpose buffer that stores the value of the respective register
until the end of the read operation. In particular, registers that occupy
more than one byte are frozen when the first byte is read. With the
exception of the uC_Status_bytes, the L64724 clears all the bits in the
Group 3 registers to 0 after a software or a hardware reset. The
uC_Status_bytes are cleared through hardware reset or the Reset_Mode
bit, located in Group 5, APR 520, bit 1. For a definition of software reset,
see Group 4, APR 55, FEC_RST and DEMOD_RST.
addresses and fields of the Group 3 registers.
Group 3: Status Registers
Reed-Solomon Uncorrected Error Count high byte, UEC[15:8]
XCTR_IN
Reed-Solomon Corrected Error Count high byte, CEC[15:8]
Reed-Solomon Uncorrected Error Count low byte, UEC[7:0]
Active
Reed-Solomon Corrected Error Count low byte, CEC[7:0]
uC_
D6
Viterbi Bit Error Rate Count high byte, VBERC[15:8]
Viterbi Bit Error Rate Count low byte, VBERC[7:0]
NCO Frequency Deviation, CAR_NCOF[23:16]
NCO Frequency Deviation, CAR_NCOF[15:8]
NCO Frequency Deviation, CAR_NCOF[7:0]
AGC Loop Voltage Meter, PWR_LVL[7:0]
Reserved
D5
CAR_LC Reserved
D4
RQ Read Back, RQ[5:0]
RI Read Back, RI[5:0]
Reserved
D3
D2
S3
Table 3.4
D1
S2
shows the
Chip_ID
D0
S1
3-23