L64724 LSI Logic Corporation, L64724 Datasheet - Page 52

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-22
APR
APR
2
3
uC_I7
D7
D7
D6
uC_I6
Reserved
TL_CL_FS_LL
TL_CL_FS_UL
The following register diagram shows the bit organization of STS[31:24].
The microcontroller interrupt register (uC_I) bits are reset after a
hardware reset. They are also reset each time the register byte is read.
The definition of each interrupt bit can be determined by the microcode.
The interrupts are user-defined.
L64724 Registers
D6
D5
uC_I5
Reserved
D5
Reserved
These bits are reserved for LSI Logic internal use only.
The bits, when read, return a value of zero.
Frequency Sweep Lower Limit Reached
The L64724 sets the TL_CL_FS_LL bit when the lower
limit of the Timing Loop Frequency Sweep is
reached.
Frequency Sweep Upper Limit Reached
The L64724 sets the TL_CL_FS_UL bit when the upper
limit of the Timing Loop Frequency Sweep is
reached.
TL_CL_FS_UL Definition
TL_CL_FS_LL Definition
D4
uC_I4
0
1
0
1
D4
STS[23:16]
STS[31:24]
D3
Frequency Sweep Status Unchanged
Frequency Sweep Lower Limit Reached
Frequency Sweep Status Unchanged
Frequency Sweep Upper Limit Reached
uC_I3
D3
D2
uC_I2
D2
TL_CL_FS_LL TL_CL_FS_UL
D1
uC_I1
D1
D0
uC_I0
[23:18]
D0
17
16