L64724 LSI Logic Corporation, L64724 Datasheet - Page 208

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

A.1 Serial Bus Protocol Overview
A-2
The multimaster serial bus interface has two signal lines—D[1] (Serial
Data) and D[0] (Serial Clock)—that are connected to the bus as shown
in
when the bus is not in operation.
Figure A.1
Serial Host Interface mode is selected when the HOST_MODE input pin
is deasserted (LOW). In Serial Host Interface mode, data is transferred
on the D[1] pin, synchronized to a serial clock that is input on the LSB
of the Host Data Bus, D[0]. The serial data clock can have a maximum
frequency of 400 kHz. The Host Data Bus pins D[3:2] are used to input
the two LSBs of the slave address, which the serial bus protocol requires.
The slave address definition is shown below:
Figure A.2
The bus master always generates the clock and cycle start and stop
conditions.
using the Serial Bus Protocol.
Programming the L64724 Using the Serial Bus Protocol
Figure
0
Serial Bus Compliant Device
A.1. External pullup resistors are required to hold the bus HIGH
0
Figure A.3
Serial Bus Architecture
7-Bit Slave Address for the L64724 Serial Bus
0
gives an overview of the Read and Write cycles
1
Serial Bus Compliant Device
1
D[3]
D[2]
5.0 V
D[1]
D[0]