L64724 LSI Logic Corporation, L64724 Datasheet - Page 24

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

2.2 Channel Clock Interface
2.3 Phase-Locked Loop (PLL) Interface
2-4
The Channel Clock interface consists of the clock and crystal oscillator
signals.
CLK
XOIN
XOOUT
The PLL circuitry multiplies the external clock signal by 2, 3, or 4 times
the symbol rate, based on the Viterbi code rate.
LCLK
LP2
PCLK
PLLAGND
L64724 Signal Definitions
IVIN/QVIN Input Clock
CLK is a positive, edge-triggered clock that strobes input
data to the L64724.
Crystal Oscillator In
The XOIN pin is used for a crystal oscillator or external
reference clock input.
Crystal Oscillator Out
The XOOUT pin is the crystal oscillator output pin.
Decimated Clock Output
The L64724 internal clock generation module generates
the LCLK signal. LCLK is derived from CLK by dividing
by the value of the CLK_DIV2 parameter (Group 4, APR
22 and 23).
Input to VCO
The LP2 signal is the input to the internal voltage-
controlled oscillator. It is normally connected to the output
of an external RC timing circuit.
PLL Clock Output
The L64724 internal PLL clock synthesis module
generates the PCLK signal. The CLK signal drives the
PLL. The PLL clock synthesis module can be configured
to generate a PCLK rate that is appropriate for all data
rates.
PLL Analog Ground
PLLAGND is the analog ground pin for the PLL module
and is normally connected to the system ground plane.
Output
Output
Output
Input
Input
Input
Input