L64724 LSI Logic Corporation, L64724 Datasheet - Page 242

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table B.8
B-28
(Sheet 3 of 4)
APR
[5:0]
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
SNR_EST
ADC_BPS
Reserved
SWP_
SWAP
SWP_
SWAP
CAR_
CLK_
D7
High Data Rate Register Values (Cont.)
CLK_LAMBDA_SEL[3:0]
Clock Loop Lambda,
ERROR_
ERROR_
PWRP_
OB_2C
L64724 Application Notes
SWAP
SWAP
CAR_
CLK_
TRI
D6
Carrier Loop Filter Initialization, CAR_LF_INIT[23:16]
Clock Upper Sweep Limit, CLK_USWL[15:8]
Clock Lower Sweep Limit, CLK_LSWL[15:8]
Clock Upper Sweep Limit, CLK_USWL[7:0]
Clock Lower Sweep Limit, CLK_LSWL[7:0]
ADC_PD
External Control Output Bits, XCTR[3:0]
AUTO_
Clock Sweep Rate, CLK_SWR[15:8]
AUTO_
Clock Loop Bias, CLK_BIAS[23:16]
CAR_
Clock Sweep Rate, CLK_SWR[7:0]
CLK_
SWP
SWP
Clock Loop Bias, CLK_BIAS[15:8]
Clock Loop Bias, CLK_BIAS[7:0]]
D5
Clock Loop Bias, CLK_BIAS[30:24]
LOCK_
served
LEN
FP_
Re-
D4
Reserved
Reserved
Reserved
Reserved
PWRP
AGC_
CLK_
SEL
D3
Clock Loop Mu, CLK_MU_SEL[3:0]
served
CAR_
PED_
SEL
Re-
D2
Reserved
DEMOD
OPEN
OPEN
CAR_
CLK_
_RST
D1
ALPHA_
CAR_
CLK_
CLK_
FEC_
RST
SEL
SW
SW
DO
HEX
AA
A0
FA
C7
05
65
0F
00
06
00
01
83
12
38
00
00
00
00
14