L64724 LSI Logic Corporation, L64724 Datasheet - Page 265

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

XCTR[1] (SCLK)
XCTR[0]
Serial_A
Serial_C[1:0]
Serializer Interface Signals and Configuration Registers
XCTR[1] is a bit in the Group 4, APR 55 register that
controls the SCLK signal on the XCTR_OUT[1] pin.
SCLK operates at a maximum of 394.74 kHz and is
obtained from a divide by 38 counter operating at the rate
of the crystal clock connected to the L64724. If the crystal
is at 15 MHz, the SCLK signal is at 15 MHz divided by
38 (394.74 kHz.) For a 10 MHz crystal, SCLK is
263.16 kHz.
(SDATA)
XCTR[0] is a bit in the Group 4, APR 55 register that
controls the SDATA signal on the XCTR_OUT[0] pin.
SDATA is the serial data output within the 3-wire
interface.
The Serial_A bit indicates whether the output pins
XCTR_OUT[2:0] are to be controlled directly as
programmed in the Group 4 register External Control
Output Bits, XCTR[2:0], or by the serializer module with
data from the TXSD, STXD, and TXED registers. When
the bit is 0 (the default), it indicates that control is as
dictated by XCTR[2:0].
Serial Transmission Control Bit C
The Serial_C[1:0] bits control whether a serial 2-wire or
a 3-wire protocol is used to serialize data. The following
table outlines the options:
Serial_C[1:0]
0
0
1
1
0
1
0
1
Selected Function
2-wire serial interface
3-wire interface, ENABLE HIGH for
all valid data
3-wire interface, ENABLE HIGH for
1 clock cycle at the start of data
transfer
3-wire interface, ENABLE HIGH for
1 clock cycle at the end of data
transfer
C-3