L64724 LSI Logic Corporation, L64724 Datasheet - Page 225

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Group 4, APR 2 – Set to 0x06.
Set the IMQ bit (D7) to either 0 or 1, clear the DVB_DSS bit (D6) and
the QB bit (D5) to 0. Based on Table 4.2, set PLL_T[4:0] (D4 to D0) to
0x06.
Group 4, APR 3 – Set to 0x18.
Clear the Viterbi Code Rate[2:0] bits (D7 to D5) to 0 for rate 1/2, set the
TEI bit (D4) to 1, set the SYNC2_MOD bit (D3) to 1, clear bit D2 to 0,
and based on Section 4.3, clear the PLL_M[1:0] bits (D1 to D0) to 0.
Group 4, APR 4 – Set to 0x40.
Since the Viterbi code rate is 1/2, based on the graph shown in
Figure 6.4,
VMBEC/VMDC1 establishes a valid decision threshold over the entire
SNR range.
VMDC1.
Equation B.7
Choosing VMDC1[7:0] = 64 (0x40) yields a value of 30 (0x1E) for
VMBEC[7:0].
Group 4, APR 5–7 – Set to 0x0F0000.
The VMDC2[23:0] bits select a second window. The VMDC2[23:0] value
controls the window size over which Viterbi errors are counted. The
VMDC2[23:0] value is used for calculating the BER, not for the
auto-synchronization that is controlled by the VMDC1[7:0] bits. In this
example, choose a window size of 3.932 x 10
which is approximately equal to 0x0F0000
Set Group 4, APR 5 to 0x00, set Group 4, APR 6 to 0x00, and set
Group 4, APR 7 to 0x0F.
QPSK Demodulator and FEC Configuration Example: High Data Rates
0.24
=
128 VMBEC
--------------------------------------------- -
for a E
256 VMDC 1
Equation B.7
b
/N
o
+
= 4.0 (E
32
shows the relationship between VMBEC and
s
/sigma^2 = 7.0), a choice of 0.24 for
6
bits = VMDC2[23:0] x 4,
B-11