L64724 LSI Logic Corporation, L64724 Datasheet - Page 98

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3-68
Set to 1
AGC_CLK_SEL
Reserved
CLK_OPEN
CLK_SW
L64724 Registers
Section 5.6, “Timing Clock Recovery,” page
information on timing sweep.
Set to 1
This bit must be set to 1 for proper operation.
Sigma-Delta Clocking Select
When the AGC_CLK_SEL bit is 1, the Sigma-Delta
module integrates the value continuously at the sampling
frequency over all samples. When the bit is 0, the Sigma-
Delta module operates on valid symbols only.
Reserved
This bit is reserved.
Clock Loop Open
Set the CLK_OPEN bit to disable the clock loop. The
clock loop integrator maintains its current value. When
the bit is 0, the clock loop operates normally.
Sweep Enable for Clock Loop
Set the CLK_SW bit to enable the Clock acquisition
sweep generator.
CLK_AUTO_SWP Sweep Mode
AGC_CLK_SEL
CLK_OPEN
CLK_SW
0
1
0
1
0
1
0
1
Definition
Enable the Clock Loop
Disable the Clock Loop
Definition
Sweep mechanism off
Sweep mechanism on
Clocking Select
Use valid symbols only
All samples used for Sigma-Delta
Manual sweep control by user
Automatic internal sweep control
5-8, for more
4
3
2
1
0