L64724 LSI Logic Corporation, L64724 Datasheet - Page 64

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table 3.5
3-34
(Sheet 1 of 4)
APR
[5:0]
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
Reserved
Set to 1
IMQ
Viterbi Code Rate, VCR[2:0]
D7
Group 4 Register Map
Reserved
Reserved
Reserved
Group 4 registers are not affected by reset—the bit values are random
immediately after power-up and retain their last known value after any of
the three reset operations as shown in
Affects Registers.” Table 3.5
Group 4 registers.
L64724 Registers
Auto Rate
Reserved
DVB_
DSS
D6
Viterbi Max Data Bit Count 2, VMDC2[15:8], middle byte
Viterbi Max Data Bit Count 2, VMDC2[23:16], high byte
Viterbi Max Data Bit Count 2, VMDC2[7:0], low byte
Viterbi Maximum Bit Error Count[7:0], Rate 1/2
Viterbi Maximum Bit Error Count[7:0], Rate 2/3
Viterbi Maximum Bit Error Count[7:0], Rate 3/4
Viterbi Maximum Bit Error Count[7:0], Rate 5/6
Viterbi Maximum Bit Error Count[7:0], Rate 6/7
Viterbi Maximum Bit Error Count[7:0], Rate 7/8
Viterbi Max Data Bit Count 1, VMDC1[7:0]
Sync Status Select,
QB
OF
D5
Reserved
SSS[1:0]
Synchronization Word[7:0]
TEI
D4
shows the addresses and fields of the
SYNC2_
IMQ_EN
MOD
Sync States Acq,
D3
PLL_N[5:0]
PLL_S[5:0]
SSA[1:0]
Section 3.2, “Reset and How it
PLL_T[4:0]
Reserved
Reserved
Bypass
DI_
D2
Sync States Track,
D1
PLL_M[1:0]
SST[1:0]
L[1:0]
DO