L64724 LSI Logic Corporation, L64724 Datasheet - Page 96

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.38 Clock Synchronizer Sweep Lower Limit
3.6.39 Clock Loop Bias (Group 4: APR 49 to 52)
3-66
(Group 4: APR 47 and 48)
Read/Write: R/W
CLK_LSWL
Program the CLK_BIAS[30:0] register with values that set the
parameters of the clock recovery loop. For details, see
“Timing Loop Sweep Equations and Timing Loop Bias,” page 5-11.
Read/Write: R/W
Reserved
L64724 Registers
APR
APR
APR
APR
APR
APR
47
48
49
50
51
52
Reserved
D15
D15
D23
D30
D7
D7
Clock Sweep Lower Sweep Limit
Program the CLK_LSWL[15:0] register to set the lower
limit of the frequency sweep. For details, see
5.6.1.1, “Timing Loop Sweep Limits,” page 5-10.
CLK_LSWL[15:0] is a two’s-complement number.
Reserved
You must set the Reserved bit to 0 for normal operation.
CLK_BIAS[23:16]
CLK_LSWL[15:8]
CLK_BIAS[15:8]
CLK_LSWL[7:0]
CLK_BIAS[7:0]
CLK_BIAS[30:24]
Section 5.6.1.2,
Section
[15:0]
D16
D24
D0
D8
D0
D8
31