L64724 LSI Logic Corporation, L64724 Datasheet - Page 237

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Group 4, APR 54 – Set to 0x00.
Set the bits in the Demodulator Configuration register (APR 54) as
shown in
Table B.6
Group 4, APR 55 – Set to 0x00.
Set the bits in the External Output Control Bits and Reset register
(APR 55) as shown in
Table B.7
Group 4, APR 56–57 - Set to 0x00.
Group 4, APR 58 – Set to 0x14.
QPSK Demodulator and FEC Configuration Example: High Data Rates
Bits
Bits
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D2
D1
D0
to
to
Setting
Setting
0b0000
0b00
Table
0
0
0
0
0
0
0
0
0
0
Demodulator Configuration Register Bits
External Output Control Bits and Reset Register Bits
B.6.
DEMOD_RST No reset for demodulator
CLK_ALPHA_SEL
XCTR[3:0]
FEC_RST
FP_LOCK_LEN
Acronym
ADC_BP
OB_2C
PWRP_TRI
SNR_EST
Acronym
Reserved
ADC_PD
PWRP
Table
B.7.
Meaning
Enable ADCs
Input is offset-binary format
Corresponding output pin = VSS
No reset for FEC
Meaning
Enable SNR estimator
PWRP not 3-stated
A/D normal operation
Normal (long) window for phase lock
PWRP pin in normal mode
Clear these bits to 0 for normal mode
Alpha value = 0.43
B-23