L64724 LSI Logic Corporation, L64724 Datasheet - Page 227

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Group 4, APR 19 – Set to 0x84.
Select the register bits according to the following table.
A DF gain of one is chosen because no decimation filter was used.
Group 4, APR 20 – Set to 0x01.
Clear bits D7 through D5 to 0. Clear the PD bit (D4) to 0 for normal
operation. Clear bits D3 to D1 to 0. Set the MF_20_35 bit (D0) to 1 for
a matched filter roll-off factor of 0.35.
Group 4, APR 21 – Set to 0x00.
Clear the PCLK_INV bit (D7) to 0 for a non-inverted PCLK output. Clear
the PLL_BP bit (D6) to 0 to enable the internal PLL to generate the A/D
clock. Clear the LCLK_OFF bit (D5) to 0 to turn off the LCLK signal.
Clear the CLK_DIV1[4:0] bits (D4 to D0) to 0 because the internal PLL
is used.
Group 4, APR 22 – Set to 0x00.
Set APR register 22 to 0x00, because the CLK_DIV2[7:0] bits are
unused when the internal PLL has been selected.
Group 4, APR 23 – Set to 0xC0.
Set the DC_Offset_On_Off[1] bit (D7) to 1 to cause the DC offset
compensation after the ADC to be activated. Set the
DC_Offset_On_Off[0] bit (D6) to 1 to cause the noise feedback to the
compensation circuit to be selected. Clear the D5 bit to 0. Clear the
CLK_DIV2[12:8] bits (D4 to D0) to 0, because the CLK_DIV2[12:8] bits
are unused when the internal PLL has been selected.
QPSK Demodulator and FEC Configuration Example: High Data Rates
D7 to D5
D4 to D3
D2 to D0
Bits
Setting
0b100
0b100
0b00
DF_RATIO[2:0]
DF_GAIN[1:0]
DF_SELECT
Parameter
[2:0]
Meaning
No Decimation filter selected.
DF Gain = 1 (No decimation filter
used).
No decimation implemented.
B-13