L64724 LSI Logic Corporation, L64724 Datasheet - Page 87

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.23 Power Estimation Bandwidth and I/Q DC Offset
(Group 4: APR 25)
This register sets the reference power level for the analog-to-digital
converter. For details on setting this register, see
Range and Power Reference,” page
unsigned number.
This register is used to enable internal DC offset compensation on the
I and Q signals and sets the power estimation bandwidth.
Read/Write: R/W
Reserved
INT_DC
PWR_BW
Group 4: Configuration Registers
APR
25
D7
Reserved
The Reserved bits must always be cleared to 0, and will
produce random results when read.
Internal DC Offset Compensation on I and Q
Set the INT_DC bit to 1 to enable internal DC offset
compensation on the I and Q signals at the output of the
matched filter.
Power Estimation Bandwidth
Program the PWR_BW[1:0] bits to set the power
estimation bandwidth. For more information see
Section 5.8.2, “Power Control Loop,” page 5-21.
PWR_BW[1:0]
0
0
1
1
INT_DC
Reserved
0
1
0
1
0
1
5-20. PWR_REF[7:0] is a positive,
Symbol Rate (MHz)
D3
Definition
Disabled
Enabled
20–45
10–20
5–10
INT_ DC
2–5
Section 5.8.1, “ADC
D2
PWR_BW[1:0]
D1
D0
[7:3]
[1:0]
3-57
2