L64724 LSI Logic Corporation, L64724 Datasheet - Page 238

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B-24
Group 4, APR 59–61 – These registers are used to communicate on a
serial bus to the tuner using the XCTR[3:0] output pins. Refer to
Appendix C for details on programming the SPI interface.
Group 4, APR 62 – Set to user preference.
Set the bits in the Group 4, APR 62 register as shown in the following
table.
Group 4, APR 63 – Set to 0x63.
Clear the FMODE bit (D7) to 0. Set the SPI_CLK_AND bit (D6) to 1 to
AND the SPI byte clock and the DVALIDOUT signal. Clear the
SPI_MODE_A_B bit to 0 for Mode A. Set the SPI_N[3:0] bits to 0x03
because the Viterbi Code Rate is 3/4.
Group 4, APR 64–65 – Set to 0x3200.
Set the SPI_GAIN[9:0] to 50 (0x32) because the oversampling ratio (OR)
is between 2 and 4.
L64724 Application Notes
Bits
D7
D6
D5
D4
D1
D0
to
to
Setting
0b0100
–
–
–
Serial_C[1:0]
SPI_M[3:0]
Acronym
Serial_B
Serial_A
Meaning
See
Serializer, for more details.
See
Serializer, for more details.
Denominator of Viterbi Code Rate = 4
(rate = 3/4)
See
Serializer, for more details.
Appendix C, Programming the
Appendix C, Programming the
Appendix C, Programming the