L64724 LSI Logic Corporation, L64724 Datasheet - Page 102

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.43 Reserved (Group 4: APR 56 to 58)
3-72
FEC_RST
Read/Write: R
Reserved
L64724 Registers
APR
56
57
58
D7
time the microprocessor writes a 1 to this bit. For
additional details, see
Register Bits,” page
FEC Decoder Software Reset
The L64724 resets the internal datapath and control
modules for the FEC portion of the device when the
FEC_RST bit is set to 1. The L64724 also resets the FEC
processing unit and state machines to their initial states.
The demodulator module is not affected. The bit does not
need to be cleared back to 0 to complete the reset. The
L64724 issues a single reset pulse each time the
microprocessor writes a 1 to this bit. For additional
details, see
Bits.”
Reserved Bits
The Reserved bits are for internal use only. The APR 56
and 57 bits return a value of 0x00 when read, and
APR 58 returns a value of 0x14 when read.
DEMOD_RESET Definition
FEC_RST
0
1
0
1
Section 3.10, “Reset Effect on Register
Reserved = 0x00
Reserved = 0x14
Reserved - 0x00
No Reset
L64724 Issues a Demodulator Reset
Definition
No Reset
L64724 Issues an FEC Reset
3-82.
Section 3.10, “Reset Effect on
Reset Value: 0x00
D0
[7:0]
0