L64724 LSI Logic Corporation, L64724 Datasheet - Page 45

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

APR
2
D7
The following register diagram shows the bit organization of SMR[23:16].
Descriptions of the fields follow the register diagram. The L64724 sets all
the bits in SMR[23:16] to 0 after a software or a hardware reset.
D6
Reserved
TL_FS_LL_IE Frequency Sweep Lower Limit Reached
TL_FS_UL_IE Frequency Sweep Upper Limit Reached Interrupt
Group 2: System Mode and System Status Registers
D5
Reserved
Reserved
The Reserved bits are for LSI Logic internal use only and
must always be cleared to 0.
Interrupt Enable
The microprocessor sets the TL_FS_LL_IE bit to enable
an interrupt when the Timing Loop Frequency Sweep has
reached its lower limit. The L64724 always sets the
TL_FS_LL bit in the STS register when this condition
occurs.
Enable
The microprocessor sets the TL_FS_UL_IE bit to enable
an interrupt when the Frequency Sweep has reached its
upper limit. The L64724 always sets the TL_FS_UL bit in
the STS register when this condition occurs.
TL_FS_UL_IE Definition
TL_FS_LL_IE Definition
D4
0
1
0
1
SMR[23:16]
D3
Disable Interrupt for Frequency Sweep
Upper Limit Reached
Enable Interrupt for Frequency Sweep
Upper Limit Reached Detect
Disable Interrupt for Frequency Sweep
Lower Limit Reached Detect
Enable Interrupt for Frequency Sweep
Lower Limit Reached Detect
D2
TL_FS_LL_IE TL_FS_UL_IE
D1
D0
[23:18]
3-15
17
16