L64724 LSI Logic Corporation, L64724 Datasheet - Page 99

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.41 Demodulator Configuration Register (Group 4: APR 54)
Read/Write: R/W
APR
54
SNR_EST
D7
PWRP_TRI
This register contains the control bits that configure the L64724
Demodulator logic.
SNR_EST
PWRP_TRI
ADC_PD
Group 4: Configuration Registers
D6
ADC_PD
D5
SNR Estimator On/Off
The SNR_EST bit enables or disables the SNR Estimator
circuit.
PWRP Signal 3-state Control
The PWRP_TRI bit, when set, forces the PWRP output
pin to a 3-state condition.
AD Converter Power-Down
The ADC_PD bit, when set to 1, turns off the AD
Converter module to minimize power consumption. No
data processing can occur during power-down. The AD
Converter operates at full power when the ADC_PD bit is
0. When the AD Converter experiences a wakeup
(ADC_PD bit changes from 1 to 0), apply a reset pulse
to the L64724 before processing data.
FP_LOCK_
PWRP_TRI
SNR_EST
ACD_PD
LEN
D4
0
1
0
1
0
1
PWRP
D3
Definition
ADC operates normally
ADC in Power Down Mode
PWRP Output Pin
SNR Estimator
D2
Normal
3-State
Reserved
Off
On
D1
ALPHA_
CLK_
SEL
D0
3-69
7
6
5