L64724 LSI Logic Corporation, L64724 Datasheet - Page 130

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

4.4.2 Parallel Output Interface (SPI_On_Off = 0)
Figure 4.7
ERROROUTn
4.4.3 Serial Output Interface
4-16
FSTARTOUT
DVALIDOUT
BCLKOUT
CO[7:0]
Descrambler Parallel Output Waveforms
When the SPI_On_Off bit is 0 and the OF bit is 1, the L64724 outputs
one new data byte on the CO[7:0] pins every eight PCLK cycles, as
shown in
The FSTARTOUT signal strobe overlaps the first data byte. The L64724
provides the BCLKOUT signal as an additional strobe that has one rising
and one falling edge per valid CO[7:0] data byte. The L64724 asserts the
BCLKOUT signal in the middle of the decoded data bytes, so the device
that receives the output from the L64724 can latch data at the BCLKOUT
rate instead of at the PCLK rate.
Note that due to the use of a constant sampling frequency and the
internal demodulator architecture, the output data stream in the parallel
output interface mode contains gaps (when DVALIDOUT is LOW.) The
distribution and position in time of the gaps are governed mainly by the
ratio of sampling frequency and symbol rate chosen. Gaps can occur at
any time in the output data stream.
To observe the output of the entire decoding pipeline in serial format,
clear the SPI_On_Off and OF configuration bits to 0.
When the OF bit (Group 4, APR 17) is 0 (Serial Channel Output Mode),
the L64724 outputs data bit serially on the CO[0] pin, as shown in
Figure
Channel Interfaces and Data Control
Byte 0 Byte1 Byte 2
Message
4.8.
Figure
N = Code Word Length
4.7.
Gap
Check Bytes
Message