L64724 LSI Logic Corporation, L64724 Datasheet - Page 8

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Tables
viii
A.6
B.1
C.1
C.2
C.3
D.1
D.2
E.1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.1
4.2
4.3
4.4
5.1
5.2
5.3
5.4
5.5
7.1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Contents
Burst Read or Single Read Cycle from Slave
AGC Loop Control
2-Wire Compliant Interface
3-Wire Interface
28-Bit Write Using 3-Wire Mode
ADC Connections for L64724
ADC Board Level Interface
Registers Shared Between the Host uP and L64724 mC
Register Overview
Group 2 System Mode Register Map (Write-Only)
Group 2 System Status Register Map (Read-Only)
Group 3 Register Map
Group 4 Register Map
Group 5 Register Map
Reset Map
Parameters for Crystal Clock (CLK) = 15 MHz
Parameters for Crystal Clock (CLK) = 4 MHz
Input Configuration
Output Selection
Decimation Procedure
Decimation Results
Roll-Off Factor
PED Gain For Carrier Loop
PWR_BW as a Function of Symbol Rate
Puncture Patterns for Various Code Rates
L64724 Absolute Maximum Rating (Referenced to V
L64724 Recommended Operating Conditions
L64724 Capacitance
L64724 Pin Description Summary
L64724-75 AC Timing Parameters with Microcontroller
Disabled
L64724-75 AC Timing Parameters with Microcontroller
Enabled
L64724-90 AC Timing Parameters with Microcontroller
Disabled
L64724-90 AC Timing Parameters with Microcontroller
Enabled
DC Characteristics of the L64724
SS
)
3-10
3-17
3-23
3-34
3-77
3-83
4-13
4-14
5-19
5-21
8-11
8-12
8-14
C-5
C-7
C-8
D-2
D-3
A-8
B-3
E-2
3-2
4-5
4-8
5-4
5-5
5-7
7-3
8-2
8-2
8-2
8-3
8-4
8-9