L64724 LSI Logic Corporation, L64724 Datasheet - Page 257

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table B.11
Group 4, APR 55 – Set to 0x00.
Set the bits in the External Output Control Bits and Reset register
(APR 55) as shown in
Table B.12
Group 4, APR 56 57 - Set to 0x00.
Group 4, APR 58 - Set to 0x14.
Group 4, APR 59–61 – These registers are used to communicate on a
serial bus to the tuner using the XCTR[3:0] output pins. Refer to
Appendix C for details on programming the SPI interface.
Group 4, APR 62 – Set according to user preference.
QPSK Demodulator and FEC Configuration Example: Low Data Rates
D2 to
Bits
D7
D6
D5
D4
D3
D1
D0
D5 to D2
Bits
D7
D6
D1
D0
Setting
0b00
0
0
0
0
0
0
Demodulator Configuration Register Bits
External Output Control Bits and Reset Register Bits
Setting
0b0000
0
0
0
0
CLK_ALPHA_SEL
FP_LOCK_LEN
PWRP_TRI
SNR_EST
Acronym
Reserved
ADC_PD
Table
PWRP
DEMOD_RST No reset for demodulator
XCTR[3:0]
FEC_RST
Acronym
ADC_BP
OB_2C
B.12.
Meaning
Enable SNR estimator
PWRP not 3-stated
A/D normal operation
Normal (long) window for phase lock
PWRP pin in normal mode
Clear these bits to 0 for normal mode
Alpha value = 0.43
Meaning
Enable ADCs
Input is offset-binary format
Corresponding output pin = VSS
No reset for FEC
B-43