HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1002

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM)
The PCI arbiter interrupt mask register (PCIAINTM) sets interrupt masks for the individual
interrupts that occur due to errors generated during PCI transfers performed by other PCI devices
when the PCIC is operating as the host with the arbitration function. It is a 32-bit register that is
readable and writable from both the peripheral bus and the PCI bus. Each bit is set to 0 to disable
the respective interrupt, or 1 to enable that interrupt.
The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset.
Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits
when writing.
Rev.4.00 Oct. 10, 2008 Page 902 of 1122
REJ09B0370-0400
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
Initial value:
Initial value:
Initial value:
Initial value:
PCI-R/W:
PCI-R/W:
PCI-R/W:
PCI-R/W:
Bit:
Bit:
Bit:
Bit:
31
23
15
—
—
—
—
R
R
R
R
R
R
R
R
0
0
0
7
0
30
22
14
—
—
—
—
R
R
R
R
R
R
R
R
0
0
0
6
0
MST_BRKN
R/W
R/W
29
21
13
—
—
—
R
R
R
R
R
R
0
0
0
5
0
TGT_BUSTO MST_BUSTO
R/W
R/W
28
20
12
—
—
—
R
R
R
R
R
R
0
0
0
4
0
TGT_ABORT MST_ABORT
R/W
R/W
R/W
R/W
27
19
11
—
—
R
R
R
R
0
0
0
3
0
R/W
R/W
26
18
10
—
—
—
R
R
R
R
R
R
0
0
0
2
0
DPERR_WT
R/W
R/W
25
17
—
—
—
R
R
R
R
R
R
0
0
9
0
1
0
DPERR_RD
R/W
R/W
24
16
—
—
—
R
R
R
R
R
R
0
0
8
0
0
0