HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 769

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
When Using the DMAC: When an external clock source is used as the serial clock, the transmit
clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is
updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles
after SCTDR1 is updated. (See figure 15.26)
When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as
the activation source with bits RS3 to RS0 in CHCR.
When Using Synchronous External Clock Mode:
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
• Only set both TE and RE to 1 when external clock SCK is 1.
TDRE
Note: When operating on an external clock, set t > 4.
SCK has changed from 0 to 1.
SCK
TxD
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2)
Figure 15.26 Example of Synchronous Transmission by DMAC
t
D0
D1
D2
D3
Rev.4.00 Oct. 10, 2008 Page 669 of 1122
15. Serial Communication Interface (SCI)
D4
D5
D6
REJ09B0370-0400
D7