HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 90

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data
Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait),
Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data
Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle
Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
Figure 23.59 TCLK Input Timing ........................................................................................... 1065
Figure 23.60 RTC Oscillation Settling Time at Power-On...................................................... 1065
Figure 23.61 SCK Input Clock Timing ................................................................................... 1065
Figure 23.62 SCI I/O Synchronous Mode Clock Timing ........................................................ 1066
Figure 23.63 I/O Port Input/Output Timing............................................................................. 1066
Figure 23.64 (a) DREQ/DRAK Timing ................................................................................. 1066
Figure 23.64 (b) DBREQ/TR Input Timing and BAVL Output Timing ................................ 1067
Figure 23.65 TCK Input Timing.............................................................................................. 1067
Figure 23.66 RESET Hold Timing.......................................................................................... 1068
Figure 23.67 H-UDI Data Transfer Timing............................................................................. 1068
Figure 23.68 Pin Break Timing ............................................................................................... 1068
Figure 23.69 NMI Input Timing.............................................................................................. 1068
Figure 23.70 PCI Clock Input Timing..................................................................................... 1071
Figure 23.71 Output Signal Timing......................................................................................... 1071
Figure 23.72 Output Signal Timing......................................................................................... 1072
Figure 23.73 I/O Port Input/Output Timing............................................................................. 1073
Figure 23.74 Output Load Circuit ........................................................................................... 1074
Figure 23.75 Load Capacitance−Delay Time .......................................................................... 1075
Appendix B Package Dimensions
Figure B.1
Figure B.2
Figure B.3
Appendix F Instruction Prefetching and Its Side Effects
Figure F.1
Rev.4.00 Oct. 10, 2008 Page lxxxviii of xcviii
REJ09B0370-0400
(One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) ...... 1056
2nd to 8th Data (No Internal Wait) (2) 1st Data (No Internal Wait),
2nd to 8th Data (No Internal Wait + External Wait Control) ............................. 1057
(One Internal Wait), 2nd to 8th Data (No Internal Wait + External
Wait Control) ..................................................................................................... 1058
(No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle
(One Internal Wait + One External Wait) .......................................................... 1059
(No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01) . 1060
Package Dimensions (256-pin QFP) .................................................................. 1085
Package Dimensions (256-pin BGA) ................................................................. 1086
Package Dimensions (292-pin BGA) ................................................................. 1087
Instruction Prefetch ............................................................................................ 1113