HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 904

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. User Break Controller (UBC)
Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31–
0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be
used in the channel B break conditions.
20.2.10 Break Data Mask Register B (BDMRB)
Note:
Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which
bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on
reset or manual reset.
Rev.4.00 Oct. 10, 2008 Page 804 of 1122
REJ09B0370-0400
Initial value:
Initial value:
Initial value:
Initial value:
*
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Undefined
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9
BDMB7
R/W
R/W
R/W
R/W
31
23
15
*
*
*
7
*
BDMB6
R/W
R/W
R/W
R/W
30
22
14
6
*
*
*
*
BDMB5
R/W
R/W
R/W
R/W
29
21
13
5
*
*
*
*
BDMB4
R/W
R/W
R/W
R/W
28
20
12
4
*
*
*
*
BDMB3
R/W
R/W
R/W
R/W
27
19
11
*
*
*
3
*
BDMB2
R/W
R/W
R/W
R/W
26
18
10
*
*
*
2
*
BDMB1
R/W
R/W
R/W
R/W
25
17
9
1
*
*
*
*
BDMB8
BDMB0
R/W
R/W
R/W
R/W
24
16
8
0
*
*
*
*