HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 634

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by this LSI in DDT mode.
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
1
2
3
4
5
6
Notes: "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Bus Mode and Channel Priority Order
When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to
channel 0, which has a higher priority, the channel 0 transfer is started immediately.
If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued
after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set
for channel 0.
If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one
transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for
channel 0. Channel execution alternates in the order: channel 1 → channel 0 → channel 1 →
channel 0.
An example of round robin mode operation is shown in figure 14.11.
Rev.4.00 Oct. 10, 2008 Page 534 of 1122
REJ09B0370-0400
Synchronous DRAM
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA
Transfer Source
The only memory interface on which single address mode transfer is possible in DDT mode
is synchronous DRAM.
When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
*
DACK output setting in dual address mode transfer
Transfer Direction (Settable Memory Interface)
*
*
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
Transfer Destination
*
*
Single
Single
Dual
Dual
Dual
Dual
Address
Mode
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Usable
DMAC
Channels