HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 283

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.6
The FPU supports two kinds of graphics functions: new instructions for geometric operations, and
pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the FPU ignores comparatively small values in the
partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In future version of SuperH RISC engine Family, the above error is guaranteed, but the same
result as SH7751 Group is not guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
• Inner product (m ≠ n):
• Sum of square of elements (m = n):
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the FPU exception cause field and FPU exception flag field is always
set to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit is set in the FPU
exception enable field, FPU exception handling will be executed.
⎯ Underflow (U):
⎯ Inexact exception (I): An inexact result is generated.
This operation is generally used for surface/rear surface determination for polygon surfaces.
This operation is generally used to find the length of a vector.
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,
or zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
Graphics Support Functions
Geometric Operation Instructions
2
–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)
Rev.4.00 Oct. 10, 2008 Page 183 of 1122
) + MAX (result value × 2
6. Floating-Point Unit
REJ09B0370-0400
–23
, 2
–149
)