HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 210

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. Caches
3b. Cache hit (write-through)
3c. Cache miss (copy-back/no write-back)
3d. Cache miss (write-through)
3e. Cache miss (copy-back/with write-back)
Rev.4.00 Oct. 10, 2008 Page 110 of 1122
REJ09B0370-0400
A data write in accordance with the access size (quadword/longword/word/byte) is performed
for the data field of the cache line indexed by effective address bits [13:5] and for the data
indexed by effective address bits [4:0]. A write is also performed to the corresponding external
memory using the specified access size.
A data write in accordance with the access size (quadword/longword/word/byte) is performed
for the data field indexed by effective address bits [13:5] and for the data indexed by effective
address bits [4:0]. Then, data is read into the cache line from the external memory space
corresponding to the effective address. Data reading is performed, using the wraparound
method, in order from the longword data corresponding to the effective address, and one cache
line of data is read excluding the written data. During this time, the CPU can execute the next
processing. When reading of one line of data is completed, the tag corresponding to the
effective address is recorded in the cache, and 1 is written to the V bit and U bit.
A write of the specified access size is performed to the external memory corresponding to the
effective address. In this case, a write to cache is not performed.
The tag and data field of the cache line indexed by effective address bits [13:5] are first saved
in the write-back buffer, and then a data write in accordance with the access size
(quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective
address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is
read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and one cache line of data is read excluding the
written data. During this time, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the effective address is recorded in the
cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written
back to external memory.