HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 517

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Burst Access: In addition to the normal DRAM access mode in which a row address is output in
each data access, a fast page mode is also provided for the case where consecutive accesses are
made to the same row. This mode allows fast access to data by outputting the row address only
once, then changing only the column address for each subsequent access. Normal access or burst
access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The
timing for burst access using fast page mode is shown in figure 13.16.
If the access size exceeds the set bus width, burst access is performed. In a 32-byte transfer, the
first access comprises a longword that includes the data requiring access. The remaining accesses
are performed on 32-byte boundary data that includes the relevant data. In burst transfer,
wraparound writing is performed for 32-byte data.
CKIO
Address
CSn
RD/WR
RAS
CASn
D31–D0
(read)
D31–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Tr1
Figure 13.16 DRAM Burst Access Timing
Row
Tr2
Tc1
d1
c1
Tc2
d1
Tc1
c2
d2
Tc2
Rev.4.00 Oct. 10, 2008 Page 417 of 1122
d2
Tc1
13. Bus State Controller (BSC)
Tc2
Tc1
c8
d8
Tc2
REJ09B0370-0400
d8
Tpc

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