HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 203

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.2
There are three cache and store queue related control registers, as shown in figure 4.1.
(1) Cache Control Register (CCR): CCR contains the following bits:
EMODE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.)
IIX:
ICI:
ICE:
OIX:
ORA:
OCI:
CB:
WT:
OCE:
CCR can be accessed by longword-size access from H'FF00001C in the P4 area and H'1F00001C
in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR
modifications must only be made by a program in the non-cached P2 area. After CCR is updated,
an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
CCR
QACR0
QACR1
31
31
31
Notes:
EMODE*
30
Register Descriptions
IC index enable
IC invalidation
IC enable
OC index enable
OC RAM enable
OC invalidation
Copy-back enable
Write-through enable
OC enable
* SH7751R only
Figure 4.1 Cache and Store Queue Control Registers (CCR)
indicates reserved bits: 0 must be specified in a write; the read value is 0.
16
IIX
15
14
12 11 10 9 8 7 6 5 4 3 2
Rev.4.00 Oct. 10, 2008 Page 103 of 1122
ICI ICE
OIX
ORA
5 4
5 4
AREA
AREA
OCI
REJ09B0370-0400
CB
2 1 0
2 1 0
WT OCE
1 0
4. Caches