HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 385

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.9
10.9.1
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The
procedure is shown below. (As the WDT does not operate when standby mode is cleared with a
reset, the RESET pin should be held low until the clock stabilizes.)
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby
2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the
3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction.
4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt.
5. When the WDT count overflows, the CPG starts clock supply and the processor resumes
6. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on
10.9.2
The WDT is used in a frequency change using the PLL. It is not used when the frequency is
changed simply by making a frequency divider switch.
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If
2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the
3. When the frequency control register (FRQCR) is modified, the clock stops. The WDT starts
4. When the WDT count overflows, the CPG starts clock supply and the processor resumes
5. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on
mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused
when the count overflows.
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
operation. The WOVF flag in the WTCSR register is not set at this time.
the clock ratio.
the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the
count overflows.
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
counting.
operation. The WOVF flag in the WTCSR register is not set at this time.
the clock ratio.
Using the WDT
Standby Clearing Procedure
Frequency Changing Procedure
Rev.4.00 Oct. 10, 2008 Page 285 of 1122
10. Clock Oscillation Circuits
REJ09B0370-0400