HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1215

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

G.1
1. Supply power to power supply V
2. Perform input to the signal lines (RESET, MRESET, MD0 to MD10, external clock, etc.) after
3. Apply power such that the voltage of power supply V
4. It is recommended to apply power first to power supply V
5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore:
G.2
1. Power off power supply V
2. There are no timing restrictions for the RESET and MRESET signal lines at power-off.
3. Cut off the input signal level for signal lines other than RESET and MRESET in the same
4. It is recommended to first power off power supply V
5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in G.3. Furthermore:
or at the same time power is supplied to V
supplied to V
⎯ Drive the RESET signal low when power is first supplied to V
power supply V
correctly if this condition is not met.
⎯ There are no time restrictions on the power-on sequence for power supply V
⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V <
sequence as power supply V
⎯ There are no time restrictions on the power-off sequence for power supply V
supply V
recommended that the power-on sequence be completed in as short a time as possible.
Vin < V
power supply V
values in the LSI’s guaranteed operation voltage range (V
ms (max.), as shown in figure G.2. The product may be damaged if this time limit is
exceeded. It is recommended that the power-on sequence be completed in as short a time as
possible.
supply V
recommended that the power-off sequence be completed in as short a time as possible.
Appendix G Power-On and Power-Off Procedures
Power-On Stipulations
Power-Off Stipulations
DDQ
DD
DD
DDQ
with regard to the LSI alone. Refer to figure G.1. Nevertheless, it is
+ 0.3 V. In addition, the time limit for the rise of either power supply V
with regard to the LSI alone. Refer to figure G.2. Nevertheless, it is
DDQ
could damage the product.
reaches 2 V. Note that the on-chip PLL circuit (PLL2) may not operate
DD
from V
DDQ
DDQ
DDQ
and I/O, RTC, CPG, PLL1, and PLL2 simultaneously.
.
≥ 1.0 V or V
DDQ
and to I/O, RTC, CPG, PLL1, and PLL2 simultaneously.
DDQ
. Applying input to signal lines before power is
DD
≥ 0.5 V, respectively, to above the minimum
Rev.4.00 Oct. 10, 2008 Page 1115 of 1122
DD
DD
G. Power-On and Power-Off Procedures
and then power supply V
is less than 1.2 V until the voltage of
DDQ
and then to power supply V
DDQ
(min.) and V
DDQ
.
REJ09B0370-0400
DD
DDQ
(min.)) is 100
DDQ
DDQ
.
and power
and power
DDQ
DD
or
.