HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 553

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the
32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of
the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register.
• Burst Read
Figure 13.39 is the timing chart for burst-read operations. For the example shown below, we
assume that two synchronous DRAMs of 512k × 16 bits × 2 banks are connected and are used
with a 32-bit data width and a burst length of 8. Following the Tr cycle, during which an
ACTV command is output, a READA command is issued during cycle Tc1. During the Td1 to
Td8 cycles, the read data are accepted on the rising edges of the external command clock
(CKIO). Tpc is the cycle used to wait for auto-precharging, which is triggered by the READA
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D31–D0
CKE
Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
TRp1
(High)
TRp2
TRp3
TRp4
TMw1
Rev.4.00 Oct. 10, 2008 Page 453 of 1122
TMw2
13. Bus State Controller (BSC)
TMw3
TMw4
REJ09B0370-0400
TMw5