HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 345

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.2.4
Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the RESET pin or due to watchdog timer overflow.
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
0
1
Note:
Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0
and 1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bit 1—Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the
cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ,
and the SQ functions are therefore unavailable. For details regarding the SH7751, see section 4.7,
Store Queues.
Bit 1: MSTP6
0
1
Initial value:
*
R/W:
Standby Control Register 2 (STBCR2)
Bit:
When the STBY bit in the STBCR register is 0
DSLP
R/W
7
0
Description
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
Transition to deep sleep mode on execution of SLEEP instruction*
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
Drives STATUS0, 1 pins to LH when in hardware standby mode
Description
SQ operating
Clock supply to SQ stopped
STHZ
R/W
6
0
—
R
0
5
—
R
4
0
Rev.4.00 Oct. 10, 2008 Page 245 of 1122
—
R
3
0
—
R
2
0
9. Power-Down Modes
MSTP6
REJ09B0370-0400
R/W
1
0
(Initial value)
(Initial value)
MSTP5
R/W
0
0