HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 532
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13. Bus State Controller (BSC)
In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each
data transfer cycle that is in response to a READ or READA command. Data are accessed in the
following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that
include the missing data are first read by the initial READ command; after that, the data between
16-bit boundaries data that include the missing data are read in a wraparound way. The
subsequently issued READA command reads the 16 bytes of data, which is the remainder of the
data between 32-byte boundaries.
Single Read: With this LSI, as synchronous DRAM is set to burst read/burst write mode, read
data output continues after the required data has been read. To prevent data collisions, after the
required data is read in Td1, empty read cycles Td2 to Td4 are performed, and this LSI waits for
the end of the synchronous DRAM operation. The BS signal is asserted only in Td1.
There are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1
to Td4.
Since such empty cycles increase the memory access time, and tend to reduce program execution
speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area
accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to
be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM
specified as the source.
Rev.4.00 Oct. 10, 2008 Page 432 of 1122
REJ09B0370-0400
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