HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 18

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xvi of xcviii
REJ09B0370-0400
Item
5.7 Usage Notes
6.5 Floating-Point
Exceptions
6.6.2 Pair Single-
Precision Data Transfer
6.7 Usage Notes
7.3 Instruction Set
Table 7.12 Floating-
Point Graphics
Acceleration Instructions
7.4 Usage Notes
8.4 Usage Notes
Page
170
182
184
185 to
188
207
207 to
209
238
Revision (See Manual for Details)
Description amended
2. If a general exception or interrupt occurs when SR.BL = 1
…
3. SPC when an exception occurs
Description amended
For information on possibilities (which differ depending on the
individual instruction), see section 9, Instruction Descriptions, in
the SH-4 Software Manual.
Description amended
The powerful geometric operation instructions, FPU also
supports high-speed data transfer instructions.
When FPSCR.SZ = 1, FPU can perform data transfer by means
of pair single-precision data transfer instructions.
Newly added
Table amended
Instruction
FRCHG
FSCHG
Newly added
Newly added
a. General exception
a. Re-execution type general exception
b. Completion type general exception or interrupt
When a general exception other than a user break
occurs, manual reset occurs. The value in EXPEVT at
this time is H'0000 0020; the value of the SPC and SSR
registers is undefined.
The PC value for the instruction in which the general
exception occurred is set in SPC, and the instruction is
re-executed after returning from exception handling. If
an exception occurs in a delay slot instruction, however,
the PC value for the delay slot instruction is saved in
SPC regardless of whether or not the preceding delayed
branch instruction condition is satisfied.
The PC value for the instruction following that in which
the general exception occurred is set in SPC. If an
exception occurs in a branch instruction with delay slot,
however, the PC value for the branch destination is
saved in SPC.
Operation
~FPSCR.FR → FPSCR.FR
~FPSCR.SZ → FPSCR.SZ
Instruction Code
1111101111111101 —
1111001111111101 —
Privileged
—
—
T Bit