HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 39

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
19.4.1 Interrupt
Operation Sequence
Figure 19.3 Interrupt
Operation Flowchart
19.6 Usage Notes
20.2.1 Access to UBC
Registers
20.3.1 Explanation of
Terms Relating to
Accesses
21.1.1 Features
Page
788
791 to
793
798
808
823
Revision (See Manual for Details)
Figure amended
Newly added
Description amended
2. Execute instructions requiring 5 states for execution after
Description amended
In this LSI, all operand accesses are treated as either read
accesses or write accesses. The following instructions require
special attention:
…
This LSI handles all operand accesses as having a data size.
The data size can be byte, word, longword, or quadword. The
operand data size for the PREF, OCBP, OCBWB, MOVCA.L,
and OCBI instructions is treated as longword.
Description amended
The high-performance user debug interface (H-UDI) is a serial
input/output interface supporting a subset of the JTAG, IEEE
1149.1, IEEE Standard Test Access Port and Boundary-Scan
Architecture. …
the memory store instruction that updated the register. As
the CPU executes two instructions in parallel and a
minimum of 0.5 state is required for execution of one
instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
Note: * IMASK: Interrupt mask bits in status register (SR)
Set BL, MD, RB bits
Branch to exception
Set interrupt source
Save SR to SSR;
save PC to SPC
in INTEVT
in SR to 1
handler
Yes
Rev.4.00 Oct. 10, 2008 Page xxxvii of xcviii
level 14 or
IMASK* =
lower?
Yes
No
Yes
interrupt?
level 13 or
Level 14
IMASK =
lower?
Yes
No
Yes
REJ09B0370-0400
No
interrupt?
IMASK =
level 0?
Level 1
Yes
No
No