HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 556

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
• Burst Write
Rev.4.00 Oct. 10, 2008 Page 456 of 1122
REJ09B0370-0400
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI,
a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the
DMAC takes place. In a burst-write operation, a WRITA command that include auto
precharging, is issued during the Tc1 cycle that follows the Tr cycle in which the ACTV
command is output. During the write cycle, the data to be written is output along with the write
command. With a write command that includes an auto precharge, precharging is of the
relevant bank of the synchronous DRAM and takes place on completion of the write
command, so no new command that accesses the same bank can be issued until precharging
has been completed. For this reason, the Trwl cycles are added as a period of waiting for
precharging to start after the write command has been issued. This is additional to the
precharge-waiting cycle as used in read access. The Trwl cycles delay the issuing of new
commands to the same bank. The setting of the TRWL2 to TRWL0 bits of MCR selects the
number of Trwl cycles. The data between 32-byte boundaries are written in a wraparound way.
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM
Tr
Row
Row
Row
Trw
Tc1
c1
Tc2
c2
H/L
c1
Tc3
c3
Tc4
c4
Tc5
c5
Tc6
c6
Tc7
c7
Tc8
c8
Trw1
Trw1
Tpc