HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 708

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15. Serial Communication Interface (SCI)
15.2.3
SCTSR1 is the register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to
SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCTDR1
to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to
SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1.
SCTSR1 cannot be directly read or written to by the CPU.
15.2.4
SCTDR1 is an 8-bit register that stores data for serial transmission.
When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to
SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by
writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1.
SCTDR1 can be read or written to by the CPU at all times.
SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Rev.4.00 Oct. 10, 2008 Page 608 of 1122
REJ09B0370-0400
Initial value:
R/W:
R/W:
Transmit Shift Register (SCTSR1)
Transmit Data Register (SCTDR1)
Bit:
Bit:
R/W
—
7
7
1
R/W
—
6
6
1
R/W
—
5
5
1
R/W
—
4
4
1
R/W
—
3
3
1
R/W
—
2
2
1
R/W
—
1
1
1
R/W
—
0
0
1